Principal Engineer, Design Verification — San Francisco

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.  At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.  Your Team, Your Impact As part of the Design Verification Team at Marvell, you will verify all of the circuitry that goes inside our chips for the general market and for specific customers. These chips use cutting-edge technology to facilitate data transfers at high speeds, and you will help verify that each design meets our customers’ specifications whether they’re a major telecom organization or automotive company, etc. What You Can Expect Develop verification plans for complex designs. Work on verification of Marvell’s AI/ML, Network processing, Compute, Memory Expander and Accelerated Compute SOCs and IPs. Develop the architecture for a functional verification environment, including reference models and bus-functional monitors and drivers using System Verilog and UVM methodology. Develop verification test plan and write tests using random techniques and coverage analysis, and work with designers to ensure it is complete. Develop tests and tune the environment to achieve coverage goals. Debug failures and work with designers to resolve issues. Architect, develop, and maintain tools to streamline the design of state-of-the-art multicore SoCs. Technically mentor a strong verification team across multiple geographies. Wage $238,000.00 - $248,000.00 per year. What We're Looking For Master’s degree, or foreign equivalent, in Computer Science, Electrical Engineering, or a related field and five (5) years of experience in the job offered or related occupation. Experience must include five (5) years in each of the following: • Developing complex/random verification environments using System Verilog/UVM. • Writing and executing detailed verification test-plan. • Scripting languages such as Python or Perl and EDA verification tools, as well as bug tracking and regression mechanisms. • Object-oriented design and implementation. • Verification with subsystems such as ARM/processor, memory, networking, NoC, and Cache designs. • Protocols such as PCIe, Ethernet, DDR, and HBM. • C/C++ for modeling and code development to run on ARM/processors. • Version control: CVS, Perforce, Git. • Low speed IO interfaces: SPI, UART, I2C, I3C, JTAG. • Bus/Interconnect Protocols: AXI, ACE, AHB, APB, NIC-400. • ASIC development process, tools and methodologies. • Analyzing complex systems, SoC architecture, memory and peripheral interfaces. 
This role is eligible to participate in Marvell's bonus and equity plans, including a new hire equity grant and annual equity refreshers, ensuring you are rewarded for your contributions and remain invested in the company's long-term success.
 Additional Compensation and Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. Interview Integrity  To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews. These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process. This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment. #LI-TT1